The equations modeling the DC operation of the FGMOS can be derived from the equations that describe the operation of the MOS transistor used to build the FGMOS. įor charge modification applications, the tunneling transistor (and therefore the operating FGMOS) needs to be embedded into a well, hence the technology dictates the type of FGMOS that can be fabricated. The injection transistor is connected normally and specific voltages are applied to create hot carriers that are then injected via an electric field into the floating gate.įGMOS transistor for purely capacitive use can be fabricated on N or P versions. The gates of every transistor are connected together the tunneling transistor has its source, drain and bulk terminals interconnected to create a capacitive tunneling structure. So, in terms of its DC operating point, the FG is a floating node.įor applications where the charge of the FG needs to be modified, a pair of small extra transistors are added to each FGMOS transistor to conduct the injection and tunneling operations. These inputs are only capacitively connected to the FG, since the FG is completely surrounded by highly resistive material. A number of secondary gates or inputs are then deposited above the floating gate (FG) and are electrically isolated from it. ![]() Structure A cross-section of a floating-gate transistorĪn FGMOS can be fabricated by electrically isolating the gate of a standard MOS transistor, so that there are no resistive connections to its gate. Carver Mead's adaptive retina gave the first example of using continuously-operating FG programming/erasing techniques, in this case UV light, as the backbone of an adaptive circuit technology.These researchers concentrated on the FG circuit properties instead of the device properties, and used either UV light to equalize charge, or simulated FG elements by opening and closing MOSFET switches. The νMOS, or neuron-MOS, circuit approach by Shibata and Ohmi provided the initial inspiration and framework to use capacitors for linear computations.Thomsen and Brooke's demonstration and use of electron tunneling in a standard CMOS double- poly process allowed many researchers to investigate FGMOS circuits concepts without requiring access to specialized fabrication processes.Three research accomplishments laid the groundwork for much of the current FGMOS circuit development: In 1989, Intel employed the FGMOS as an analog nonvolatile memory element in its electrically trainable artificial neural network (ETANN) chip, demonstrating the potential of using FGMOS devices for applications other than digital memory. Initial applications of FGMOS was digital semiconductor memory, to store nonvolatile data in EPROM, EEPROM and flash memory. The earliest practical application of FGMOS was floating-gate memory cells, which Kahng and Sze proposed could be used to produce reprogrammable ROM ( read-only memory). ![]() The first report of a FGMOS was later made by Dawon Kahng and Simon Min Sze at Bell Labs, and dates from 1967. ![]() The first MOSFET was invented by Mohamed Atalla and Dawon Kahng at Bell Labs in 1959, and presented in 1960. ![]() Other uses of the FGMOS include a neuronal computational element in neural networks, analog storage element, digital potentiometers and single-transistor DACs. The FGMOS is commonly used as a floating-gate memory cell, the digital storage element in EPROM, EEPROM and flash memory technologies. Usually Fowler-Nordheim tunneling and hot-carrier injection mechanisms are used to modify the amount of charge stored in the FG. Since the FG is surrounded by highly resistive material, the charge contained in it remains unchanged for long periods of time, nowadays typically longer than 10 years. These inputs are only capacitively connected to the FG. The floating-gate MOSFET ( FGMOS), also known as a floating-gate MOS transistor or floating-gate transistor, is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) where the gate is electrically isolated, creating a floating node in direct current, and a number of secondary gates or inputs are deposited above the floating gate (FG) and are electrically isolated from it. Type of MOSFET where the gate is electrically isolated
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